Conventionally, a testing apparatus which tests an electronic device (DUT: Device under Test) such as a semiconductor device supplies a signal to an electronic device with a prescribed timing. For example, a testing apparatus is provided with a timing generator which generates a timing signal for regulating the timing.
The configuration of this timing generator is shown in FIG. 6. As shown in FIG. 6, a timing generator 100 has a counter 110, a timing memory 120, an exclusive OR circuit 130, an AND circuit 140, a linearizing memory 150 and a variable delay circuit 160 as disclosed by, for example, International publication No, WO 2005/060098.
The counter 110, the exclusive OR circuit 130 and the AND circuit 140 generate a delay which is the integral multiple of the period of a given reference clock RefClk. That is, the counter 110 receives the reference clock RefClk, and outputs a counted value which is obtained by counting the pulse number of this reference clock.
The timing memory 120 receives a timing set signal TS which indicates the timing with which a timing signal is generated by the timing generator 100, and outputs to the exclusive OR circuit 130 a control signal corresponding to the higher-order bit of the timing set signal TS.
For example, the timing set TS signal is data which shows the delay amount which is required to delay the reference clock RefClk. The timing memory 120 outputs to the exclusive OR circuit 130 a quotient obtained by dividing the delay amount by the period of the reference clock RefClk.
The timing memory 120 outputs to the linearizing memory 150 a control signal which corresponds to the lower-order bit of the timing set signal.
For example, the timing memory 120 supplies to the linearizing memory 150 a delay setting data which corresponds to the remainder of a value obtained by dividing the delay amount shown by the timing signal by the period of the reference clock.
The exclusive OR circuit 130 outputs an H-logic signal when the counted value provided by the counter 110 is in agreement with the value provided by the timing memory 120 (the value of a control signal corresponding to the higher-order bit) Then, the AND circuit 140 outputs a logical product of a signal obtained by the exclusive OR circuit 130 and a reference clock.
The linearizing memory 150 stores control data which corresponds to the linearization of the delay setting data in a fine variable delay circuit 160, and outputs a delay amount signal based on the delay setting data (the control signal corresponding to the lower-order bit) to control the delay amount in the variable delay circuit 160.
The variable delay circuit 160 delays the signal outputted by the AND circuit 140 based on the delay amount signal outputted by the linearizing memory 150, and outputs the delayed signal as a timing signal.
As shown in FIG. 7, this variable delay circuit 160 has buffers 161-1 to 161-n (hereinafter simply referred to as a “buffer 161”), a multiplexer 162 and a fine delay part 170.
The plurality of buffers 161 are connected in series, and sequentially delays a signal outputted by the AND circuit 140.
The multiplexer 162 selects a signal outputted by any of the buffers 161 based on the control data (delay amount signal) provided by the linearizing memory 150 and outputs the selected data to the fine delay part 170. As a result, a delay which is the integral multiple of the delay amount in the buffer 161 is generated.
The fine delay part 170 generates a delay of which the delay step is smaller than that of the delay in the buffer 161 and of which the maximum delay is almost equal to the delay of one stage of the buffer 161. That is, this fine delay part 170 generates current Id which is proportional to a delay setting data DATA (delay amount signal) provided by the linearizing memory 150, and controls the delay amount by selecting the source current Id of a buffer 174 (mentioned later) according to this current Id.
As shown in FIG. 8, the fine delay part 170 has a DAC (Linear DA converter) 171, a BIAS (bias circuit) 172 and a delay element 173. The delay element 173 has the buffer 174 noted above and current sources 175 and 176.
The DAC 171 is capable of generating current which is larger than by k to (k+2n−1) times current Id which corresponds to a BIAS voltage applied to the current sources 175 and 176.
This DAC 171 may have a configuration shown in FIG. 9.
Specifically, in the DAC 171, switches S and current sources are paired, and a plurality of delay time converting current generating circuits 180-1 to 180-n (hereinafter abbreviated as “delay time converting current generating circuit 180”) are connected in parallel with respect to a terminal which provides a bias voltage (bias resolution). To these plurality of delay time converting current generating circuits 180, predetermined number of the current sources are connected in a manner indicated by a binary-coded number (*k,*1,*2, . . . , *2n-1), thereby amplifying the basic current at different magnifications.
The delay time setting switch S is turned ON and OFF based on the delay setting data. Each current is amplified at each power source, and the current corresponding to the delay setting data is selected and the selected current is supplied to a voltage converting circuit 190.
The BIAS 172 is current-mirror connected such that current Id flowing in the buffer 174 (current source transistor in the delay element) becomes equal to the current Id of the DAC 171. As a result, the current Id generated by the DAC 171 can be mirrored to the delay element 173 by current-mirror connection.
The buffer 174 delays a signal outputted by the AND circuit 140 (“IN” in FIG. 9), and outputs the delayed signal as a timing signal (“OUT” in FIG. 9). The current sources 175 and 176 regulate the source current of the buffer 174.
As shown in FIG. 10(a), the fine delay part 170 has a configuration in which the delay setting data DATA and the current Id are in a proportional relationship.
The relationship between the current Id supplied by the current sources 175 and 176 of the delay element 173 and the propagation delay time Tpd of the delay element 173 is hyperbolic (inverse proportional), as shown in FIG. 10(b).
As a result, the relationship between the delay setting data DATA and the propagation delay time Tpd becomes hyperbolic, as shown in FIG. (c).
Patent Document 1: WO2005/060098